This method provides a huge performance improvement, but it still has shortcomings.
For semiconductors, things that everyone takes for granted usually cause the biggest headaches, and when fundamental changes occur, the problem becomes more complicated-such as combining two chips with a process designed to maximize performance. Together.
Example: CMP used for back-end metallization in hybrid bonding. Although this is a mature process, it is not easily converted to hybrid bonding, where the pads are larger and the copper groove requirements are more stringent. The alignment accuracy of the existing flip-chip assembly bonding machine is 3 microns or higher. The industry rule of thumb estimates that the bonding pad needs to be five times more accurate than the bonding machine to obtain a sufficient yield. Non-voided bonding requires shallow and uniform copper grooves, but the depth of CMP grooves tends to increase with pad size. Reducing the hybrid bond to below 3 microns will require improvements in the CMP process.
Among them, the CMP process needs to be optimized for the pattern density effect in the bonding layer and the underlying metal layer. EV Group business development director Thomas Uhrmann pointed out that the contact pads are usually concentrated on the edge of the chip, while the rest of the chip area is blank. Therefore, in order to achieve uniform CMP performance, it may be necessary to use dummy pads. The interconnection structure below may also affect wafer shape and wafer stress.
Regardless of the pad size, higher pad density is more prone to bonding voids. In the work demonstrated at the 2020 IEEE Electronic Components and Technology Conference, Soon-Wook Kim of Imec and colleagues explained that if the spacer protrudes, it can move nearby dielectric surfaces away from each other, creating voids. However, if the pads in the dense array protrude, adjacent voids will merge to create a larger gap.
Pad design can help compensate for alignment constraints. Eric Beyne, head of the Imec 3D system integration project, explained that one method is to match the small, slightly protruding copper pads on one wafer with the wider, slightly recessed copper pads on another wafer. The size difference depends on the overlap tolerance of the bonding system. This design ensures that strong bonding that does not overlap with the dielectric can still occur, even if the smaller pad is not precisely located in the center of the target wafer. Imec also demonstrated another solution, which uses short copper wires instead of square pads, and the horizontal lines on one layer match the vertical lines on the next layer. Not only is the line less prone to sinking, but even if the overlap does not match and the "center" of the line is moved considerably, successful bonding can occur.
Figure 1: TEM hybrid Cu/SiCN and Cu/SiCN bonding. The top Cu pad is 270nm, the bottom is 400nm, and the pitch is 700nm. Source: Imec
To prevent voids and other defects, hybrid bonding requires flat and clean contact surfaces. In wafer-to-wafer bonding, you can rely on a well-controlled CMP process to provide such a surface. After that, the Xperi group completed the preparation of the target wafer through deionized water rinsing and plasma treatment. The company believes that the risk of copper oxidation at room temperature is exaggerated, so there is no need to take aggressive cleaning steps to remove any oxides.
Xperi considers oxidation at high temperatures as a more serious problem. For this reason, it focuses on reducing the temperature requirements of its process, and recently reported 200°C annealing for 1 hour.
Uhrmann said that the EV Group's bonding process chamber is not designed for deposition or etching, but uses a relatively mild plasma to change the surface reactivity. For example, when the initial dielectric bonding step uses water to pull the surfaces together and promote bonding, the surface treatment will seek to create OH groups, modify the subsurface bonding, etc.
Single chip is not clean. Although wafer-to-wafer bonding can usually rely on a clean starting surface, hybrid bonding used as part of a heterogeneous integration solution is another animal. Whether the process places a single chip directly on the target wafer or on an interposer or temporary substrate, the challenges are similar.
In die-to-wafer (or interposer) bonding, die separation is a potentially huge source of particles and other contaminants, which can lead to voids and other defects in the bonding interface. All failures discovered by the Xperi team were due to voids caused by particles, not CMP-related defects such as topography changes. Researchers at Imec are studying plasma cutting, glass carriers, and alternative protective layers to increase defect rates.
Who pays for all this? One of the most challenging issues with hybrid bonding is cost. This raises questions about where it really fits in the supply chain.
Chip manufacturers, including foundries and IDM, regard this processing as an extension of the back-end production line of the fab. Bain said that compared to other types of packaging, the equipment involved is more expensive and more automated, and the requirements for process cleanliness are much stricter.
On the other hand, a key argument for heterogeneous integration is that the integration package may contain components from multiple different companies. System integrators would rather not rely too much on specific fabs. At the same time, foundries hope to manufacture integrated packages and all component chips.
The tension between the two views creates market opportunities for OSAT. However, actually taking advantage of this opportunity is not so easy. Packaging has always been a low-profit, low-value-added business. Heterogeneous packaging requires more expensive processing, but it also adds more value. In order to be financially viable, the store needs to get some value for itself. Without it, hybrid bonding is likely to remain the exclusive domain of high-volume, single-manufacturer components.
The de-aggregation of the related binding problems of multi-chip packaging solves some problems, but it creates new problems. Mutation threats in advanced nodes, complex interactions with packet growth, and tighter tolerances can affect performance, power, and life expectancy.
An excellent overview of IC Heterogeneous Integration (HI). Regarding mold cleanliness, remember that plasma cutting and protective sacrificial coatings have proven to be "off the shelf" technologies...and the cost of this added value must be limited. All of this has brought a series of new problems/opportunities for material suppliers, OEMs and OSAT!
Cu-Sn TCB flip chip bonding with uPillar bumps (50 micron pitch) used in offshore houses in the Asia-Pacific region has a history of 25 years. 23 years ago, Motorola Semiconductor put into production in AZ. In order to use FC GaAs FET (w/bump pitch has reached 25 um), it completely changed the mobile phone by allowing sufficient bandwidth to access the network, while still keeping the packaging cost at Lower than the previous wire bonding version!
Not many fundamental improvements have been made to optimize this technology of stacked chips. Once all this CoVid nonsense is under control, we will once again base on theory instead of incremental/surface engineering to disclose the next-generation TCB optimized for Die Stacking.
The life of the TC FCB should be extended by several years until the hybrid FCB is ready for HBM etc.
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