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Portable wireless communication devices, whether mobile phones, personal digital assistants, or a combination of the two, are pushing to save more space on printed circuit boards. In the past few years, a pair of two-dimensional methods combining processors, controllers, logic, and memory has emerged. One solution designs all components on a single silicon chip, while its competitors squeeze two or more dies into various multi-chip modules. It is a system on chip (SoC) and a system in package (SiP).

So far, this has not been a fierce game. According to the Cahners In-Stat Group of Scottsdale, Arizona, SoC unit shipments reached 345 million in 1999 and are expected to reach 1.3 billion in 2004. According to Prismark Partners of Cold Spring Harbor, New York, it was completed in 2003 and nearly two-thirds of it will be used for wireless devices

But now, an evolutionary technology can put SiP into fierce competition by using the third dimension. Called system-level stacking, it packs more chips into the same circuit board area by encapsulating bare chips in a stack [see illustration]. Upward rather than outward will shorten the interconnection distance, thereby reducing delay and capacitance and increasing speed and/or reducing power requirements. Shorter interconnects also reduce noise and further improve performance.

The idea of ​​stacking chips is nothing new. Sharp Corporation of Osaka, Japan took the lead in introducing the first bare-chip flash memory and SRAM stacked chip scale package (S-CSP) for mobile phones in 1998. Today, Fujitsu, Hitachi, Mitsubishi, NEC, ASE, Toshiba, Dense-Pac Microsystems, and Amkor Technology are all producing millions of different types of S-CSP for portable communication devices.

In this typical package, two or three memory chips are stacked on top of each other, separated by a thin layer of die attach material, and connected to die bond pads on the package substrate by wires. According to Jan Vardaman, president of TechSearch International, a market research company in Austin, Texas, unit shipments of these packages reached 100 million units in 2000. She expects this number to double in 2001, and is expected to increase at a rate of 20-30% annually for at least the next two years.

Companies hoping to further integrate memory with digital signal processors (DSP), application-specific integrated circuits (ASIC) and microprocessors will not lose the advantage of stacking bare chips. Intel Corporation, located in Santa Clara, California, plans to use a new technology from Tessera Technologies Inc. of San Jose, California in the next few months to launch a stack of three to four memory chips. A stack system logically folded together. Tessera pioneered chip-scale packaging in the mid-1990s with its patented micro ball grid array (µBGA). There is now a way to connect memory chips and very fast ASICs to flexible tape, and then fold the tape to Create a thin stack. Valtronic SA of Les Charbonnières, Switzerland has folded logic, memory and passive components into a single package for hearing aids and other low-volume, high-value applications.

Coming soon is a cube system based on epoxy resin molded layers of different chips. These super stacks are mainly developed by companies such as Irwin Sensors of Costa Mesa, California, and 3-D Plus of France Booker for military and space applications. They can now be found in satellite miniature cameras and should be able to build more powerful Wearable computer.

In early April 2001, Amkor Technology Inc., located in West Chester, Pennsylvania, announced an aggressive roadmap for 3-D stacked bare chip packaging. It is one of the world's largest semiconductor packaging and testing service contract manufacturers, and it is responding to growing customer demand for more system-in-package options. Amkor has assembly plants in South Korea and the Philippines, and plans to add 3D packaging capabilities to new plants in China and Taiwan.

Amkor's 3-D stack products are the epitome of the entire industry. Bare chips are stacked in multiple combinations of wire bonding, ball grid array, and flip chip configurations. These combinations are very attractive to manufacturers like Motorola, Schaumburg, Illinois, who want to package ASICs with off-the-shelf flash memory or DRAM instead of embedding flash memory or DRAM in the ASIC itself.

Jon Woodyard, Amkor 3-D Technical Product Manager, said: “By integrating the chips in the same package, rather than in the same silicon, this is an excellent way for the company to maximize production.” This 3-D stacking also Allow the company to provide a series of packages with the same size but different functions. For example, depending on the type of equipment and the end market, the company can combine digital ASICs, analog chips, flash memory chips, and DRAM chips in different two-chip or three-chip stack arrangements in the same package, or one or two chips can be arranged in a two-dimensional manner Beside the stack. This will save the cost of creating different ASICs for each application.

In addition, manufacturers can respond to competitive threats and increase their product lines by simply stacking more chips in the package. For example, a 16Mb flash memory can be added to a 32Mb memory package, and they all fit the same 12 x 12 mm footprint. "They don't have to increase the packaging size now to make room," Woodyard said. "They are just vertical."

One technology Amkor is evaluating for inclusion in its stacking solution suite is the aforementioned Tessera Technologies folding stacking technology [see picture]. The company develops and licenses advanced packaging technologies for the semiconductor industry. It also provides design and prototyping services for chip-scale packaging. It is probably best known for the increasingly popular µBGA, which is a chip-scale package that is very suitable for folding processes and benefits from its flexible and removable or compatible components because of its excellent onboard reliability. The µBGA package has flexible S-shaped copper leads to connect the die to the solder balls and ultimately to the circuit board. The sealant in the µBGA package is an elastomer that is softer than the epoxy resin commonly used for molding, explains Phil Damberg, the company's director of product engineering and test assembly. These combined effects allow the package to bend to absorb the strain caused by the difference in thermal expansion coefficient between the chip and the printed circuit board or the flexible polyimide tape used in the folding process.

Folding the edge of the stack to the mainstream

Tessera engineers used its folding stack technology and utilized its µBGA technology to work with Intel for a year to install three to four chips in a very low package-three-chip stack less than 1 mm, and for a four-chip stack . Tessera says it can install up to 14 chips using the same method. Because its customers already have manufacturing capabilities and licenses, Tessera is helping them switch to folding stack technology, first for memory applications and then for stack systems, starting with ASICs and memory.

“For these companies, this is an exciting technology,” Tessera CEO Bruce McWilliams said enthusiastically, “because they don’t need to install a new production line for stacking. They only need to add at the end of the µBGA production line. A tool to complete the folding."

This sounds easier than it actually is. Four-chip stacking [see picture again] starts with a 40mm long rectangular double-sided polyimide tape (Kapton or Upilex), 25 or 50 microns thick. There is a metal layer on each side of the polyimide tape, which is used to fix all the leads and interconnections between the chips, similar to a printed circuit board. Flash memory, SRAM or DRAM chips undergo standard µBGA processing. Chips are fixed on tapes using silicon or epoxy-based chip connection materials, and are bonded and packaged by wire bonding. Then connect the solder balls to the pads on the tape on the bottom of the package. At the end of the production line, instead of punching out the finished single µBGA package, the strip of four chips is transferred to a two-step folding process.

First apply a layer of silicone adhesive on the back of the middle two chips. The outer two molds are folded on top of the middle two molds by special tools to create a pair of two mold stacks. More adhesive is distributed on the two stacks and then folded on each other. The tool shuttles the folded stack into a fixture, which secures the package together when the adhesive cures. The completed module is mounted on its circuit board with solder balls previously placed on soft tape.

According to Ted Tessier, vice president of advanced application development at Amkor, Tessera's folding technology enables the lowest possible package outline. The reason is that dies of the same size are stacked together without the silicon or thin film spacers required to separate the chips in a stacked chip-scale package. As with all chip-scale packaging, the planar size of the folded stack solution is only slightly larger than the largest chip in the stack.

Compared with some traditional S-CSP, another advantage of flexible tape is wiring density. S-CSP connected to a rigid FR-4 (flame retardant epoxy resin/glass cloth laminate) package substrate via a ball grid array is usually limited to 40 micron lines and spacing. This is because these substrates are derived from printed circuit board manufacturing processes, which are conducive to large panel formats and are limited in terms of lithography resolution and etching processes. In contrast, the smallest lines and spacing on soft tape is 25 µm. Since the wiring density of the tape is better than that of the ball grid array S-CSP, the folded flexible package will allow a smaller overall package footprint.

Despite these advantages, Amkor will still delay the adoption of the technology until many technical and supply chain issues are resolved. One of them is the availability and cost of double-sided polyimide tape.

Part of the reason for the higher cost of double-sided tape compared to single-sided tape is that it involves additional process steps and different production lines. Damberg said that Tessera has been working with high-volume substrate suppliers to reduce costs. Ultimately, the price will depend on how many high-volume customers choose a folding stack design, such as Intel. Tessera also told customers that for some folding and stacking applications, cheaper single-sided tape is sufficient.

Then there is the heat dissipation problem that 3D packaging is particularly facing. In a three-chip stack, the bottom chip closest to the circuit board can effectively dissipate heat, while the top, especially the middle chip in the stack, cannot. A partial solution is to place high-power chips at the bottom of the stack, because 85-90% of the total heat is dissipated through the mounting board.

Because the power consumption level is not high, this is not as serious as it seems in memory applications. Tessera Product Design and Reliability Director Young-Gon Kim pointed out that although the power consumption of each flash memory chip ranges from 0.15 W to 0.4 W "heat in standby mode. Therefore, the overall power consumption of the stacked package is much lower than the number of dies implied of."

However, Tessera engineers knew that they had to come up with more aggressive cooling strategies to accommodate higher power ASICs, which usually dissipate 10 W or more. Therefore, the company is exploring ways to optimize the thermal performance of the package by adjusting its structure and using various combinations of high thermal conductivity sealants, copper ground plates and heat sinks.

Although Intel and other Tessera customers plan to introduce memory in a folded stack package in the next few months, the aforementioned Swiss company Valtronic has been folding logic, memory, and passive components into packages for the past two years. Although Valtronic's package is higher, so far Tessera's package contains only memory, no logic, and of course no passive components.

Valtronic is a contract manufacturer with an annual output value of 50 million US dollars. It provides custom-designed folding stacking systems for customers with an annual output of less than 1 million pieces, but the output is relatively low. For example, it uses its patented 3D chip scale packaging (3D-CSP) technology to install the world’s smallest hearing aid in a 4.5 x 4.0 x 3.0 mm module, and integrates a central processing unit and a digital signal processor , An EEPROM chip and 18 passive components.

Gold is the key in Valtronic's laminated solution for high-reliability products such as cardiac defibrillators and hearing aids. The gold stud bump flip chip eliminates the chip bonding wires, reduces the circuit wiring length and minimizes the resistance, capacitance and inductance of most interconnections, and each chip can usually accommodate more than 500 connections.

Valtronic starts with 25-50 µm thick double-sided flexible polyimide strips. Like Tessera, Valtronic sometimes uses Kapton, but it also uses other types of polyimide strips, the company does not disclose its ingredients. The gold pad is deposited on the tape, covered with a non-conductive, non-silicon-based adhesive, and pressed with gold studs on the flip chip. The adhesive minimizes the thermal expansion effect between the chip and the tape, so when the polyimide tape heats up and moves relative to the silicon chip, the gold bumps and pads will also move, but they will not lose contact. The fatigue and stress associated with solder joints used in other flip chip processes are completely non-existent.

Although gold contacts provide the kind of high reliability required for medical implants, the stud bump flip chip used by Valtronic has a size limit and can only accommodate a pad pitch of up to 110 mm. In contrast, Tessera's µBGA package can provide a pad pitch of 80 mm for peripheral pads, allowing the company's customers to use smaller chips.

After the flip chip is connected to the flexible tape, the passive components are surface-mounted to the bottom. Different types and sizes of components, from flat chips up to 2 mm2 in size to cube resistors and capacitors up to 1 cm3 in size, can be installed within 1 mm of each other. To some extent, passive components are larger than active components, which ultimately determines the size of the package.

For the three-layer folding stack used to make hearing aid modules, the unfolded package starts in a cross configuration on the strip and then wraps up like a burrito. First, the bottom of the cross is laser cut from a roll of tape and folded in the middle, then the top is cut and folded down. Then the module is cut from the strip with a laser, and the potting material flows into the center of the package [see picture].

Unlike Tessera's rectangular tape strips, the layout of Valtronic can vary. Even L-shaped and S-shaped strips are possible, so the manufacturing process is similar to high-tech origami. The shape depends on the application. Gary Pinkerton, Sales and Marketing Director of Valtronic USA Inc. explained: “Usually, the final package volume requirements and component size will affect the layout. At other times, components must be isolated from other components, so we place them as far as possible. "

The miniaturization of this Swiss company is not cheap. But its customers are willing to pay for the smallest inductance and capacitance. After all, this means lower power consumption and longer battery life, which is especially important for medical implants.

As stacking technology begins to enter the mainstream, companies like Irvine Sensors Corp. have been leading competitors for several generations and have developed a technology for military and aerospace customers that can stack dozens of different chips together. Irvine Sensors does not fold tape strips with parts, but embeds the chipset in an epoxy resin matrix, similar in shape to ordinary round silicon wafers [see figure top]. The matrix can then be processed using standard wafer tools and fixtures to produce a cube system sold by Irvine Sensors under the Neo-Stack trademark. For example, the combination of four Neo-Stacks can provide a wearable computer with the function of a workstation, the size of which is equivalent to a deck of cards. Irvine Sensors is beginning to see industry interest in embedded applications for cube systems, and it is expected to begin initial production within 12-18 months.

Irvine Sensors' Neo-Stack starts with Known Good Die (KGD) and unpackaged ICs. These ICs have undergone aging and testing similar to packaged ICs to ensure high yield of finished modules. Compared with untested chips, KGD is expensive and is often avoided by companies that can tolerate the loss of some bad but cheap modules (such as flash memory or SRAM stacks). But for the complex stack of different chips that Irvine Sensors excels at, KGD is crucial.

The first step of the Neo-Stack process is to use KGD and bump I/O pads with gold or solder. The chips are then combined into separate stacked layers, each layer being slightly larger than the largest chip in the stack. Each layer is a standard size, although each layer may have different chips.

"The new stack allows us to mix and match almost any type of component, whether it's optics, microelectromechanical, electronics or optoelectronics in stacked packages," said Volkan Ozguz, Irvine Sensors Technology R&D Manager.

When the chip collides with gold or solder, the photosensitive polyimide film is spin-coated on a piece of aluminum foil, called a spacer, to align the film. A mask that matches the position of the bumps and the size of the chip to be embedded is covered on the polyimide film. After the film is exposed, the gasket film assembly is bonded to a glass epoxy-based carrier, the gasket is etched away, and the raised chip is embedded on top of the polyimide film. Potting epoxy resin fills the cavity and cures the Neo-wafer.

Next, the wafer is polished to expose the flat surface of the polyimide, and the flat bumps are flush with the surface. Metal traces are deposited to bring I/O from each layer to both sides of the stack. The metal interconnections between the chips of the same layer are deposited and then covered with a polyimide protective layer. Using a mask, through holes corresponding to the positions of bump pads on other layers can be added to create a multilayer interconnection structure.

Then grind the Neo-wafer at the bottom to the required thickness of 150-200 µm and cut into individual layers, stack these layers according to the package design, and fix them together with a 1 µm adhesive coating [see opposite bottom Part of the picture]. The stack is covered with a polyimide glass substrate, which is coated with metal on both sides and connected to the rest of the stack through through holes. Then stack the sides to expose the interconnection. At this time, add bus metal on both sides to complete the layer-to-layer interconnection, and bring all I/O signals to the top cap chip [not shown in the figure].

Using this technology, Irvine Sensors has built up to 48 layers of Neo-Stack. Ozguz pointed out that there is no basic limit to the number of layers that Neo-Stack can hold.

The heat dissipation efficiency of epoxy resin is not as good as that of silicon. Therefore, in order to improve the heat transfer between layers, blank silicon wafers are sometimes added in the open areas on the layers where smaller chips are used. Heat sinks can also be added, such as copper plates that divert heat to the sides of the stack, to provide lower thermal resistance. According to the company, this advanced technology allows Irvine Sensors to create stacks that handle 50-60 W—at least an order of magnitude higher than most 3-D packages today.

Testing and yield have always been the main stumbling blocks for stackers. The reason is simple: if there is a bad chip in the stack, it must either be replaced or the entire package must be discarded. This is not a problem when stacking commercial memory, but it is a serious problem when more expensive ASICs or CPUs are eliminated.

To solve this problem, Valtronic conducts tests at the prototype stage after each flip-chip application, and performs functional tests after adding passive components. Fully functional verification is performed again after folding. However, once production is in full swing, only the completed modules will be tested for functionality. Since Neo-Stack started with known good dies, the output is expected to be very high. In addition, each layer of Neo-Stack is individually tested after cutting. In some cases, redundant components are provided in the stack to further reduce the risk of failure.

Compared with the currently available two-layer and three-layer stacks, the Neo-Stack module is more valuable. Again, for Irvine Sensors' performance-oriented military and aerospace customers, reliability rather than cost is the key issue. They include the Defense Advanced Research Projects Agency, the Ballistic Missile Defense Organization, and NASA, for which the company has developed cube system technology for wearable computers and satellite applications.

For government suppliers, waiting for the commercial sector to develop into advanced technologies originally developed for military and space applications is tiresome, to say the least. But Ozguz believes that the trend of stacking systems will continue to move towards more complex applications. "Competitors such as Amkor, Tessera, and Sharp that provide two- or three-layer stacking are helping mainstream application designers believe that 3-D stacking is a viable approach," Ozguz said. When customers are ready to upgrade to next-generation system-level stacking solutions, Irvine Sensors will be ready to help.

The latest exploration of 3-D packaging is "The Coming of the Era of 3-D Packaging" by Larry Wu et al. The paper was published in the Proceedings of the 2000 IEEE/CPMT International Conference on Electronic Manufacturing Technology, pages 102-07.

What happens when you ask kids to design their own social robots from scratch

The robot in the picture above is called YOLO, which stands for "your own living thing." It looks weird-unlike you and I would design, if someone tells us to design a social robot, right? That's because YOLO is a robot designed by and for children. Please note that it is not adults who make the kind of robots they think children will want, but real children design from scratch.

It is not easy for children to design robots. It takes years to transform YOLO from concept to physical reality, taking into account simplicity, cost, and durability level compatible with open games. The end result is completely different, and it is also very effective in helping children tell better stories.

Human-centered robot design can be very challenging, because once you install the robot to the point where user testing is possible, the main types of changes you can easily implement are usually very small. On the other hand, if you try to get user input earlier, you can usually only conduct interviews or questionnaires or ask people to view content such as images or animations, which are not very reliable in providing useful feedback. Interact with physical robots The way.

When you start talking about children, things become more difficult because even these questionnaires are not as effective as adults. This is a big problem, because social robots may be (I think) very valuable for children as a tool for education and social development. Of course, we don’t have social robots yet, but knowing how to design robots for kids is one of the things we need to figure out early, even if it’s not the first step.

The coolest thing about YOLO is how unapologetically child-centered the whole process is; there seems to be no adult in that robot. But it takes the input of 142 children to reach this point. For those engaged in this work, YOLO is a long journey.

For more detailed information about YOLO and the thought and process behind the design, we talked with Patricia Alves-Oliveira, creator of YOLO.

IEEE Spectrum: What is your overall impression of the current generation of children's social robots?

Patricia Alves-Oliveira: Social robots seem to be a new generation of children's toys. Generally speaking, toys are the most important tools in children's lives, because while manipulating them, children learn to explore the world. Toys are the first tool children use to express their emotions and thoughts. The way we use tools and children's toys can profoundly influence and change the way we learn and experience the world. If we regard children's social robots as a new generation tool, we will feel that children can be exposed to a richer combination of games, allowing them to be stimulated in new ways that traditional toys cannot inspire. Therefore, they can experience the world in a richer way.

What kind of toy is a social robot?

Social robots may include robots for playing and robots for learning. Robots used for playing usually take the form of animals or dolls, and usually have human-like features, such as eyes and mouths. When children use robots to play, they are not only entertained, but also stimulated. For example, they learn problem-solving, conflict-resolution, and social-emotional skills while paying. This is possible because the robot can play back to them, resulting in a two-way game or a social game. The game depends not only on the children's imagination, but also on the relationship they can establish with this person's tool body system.

In contrast, robots used for learning are deliberately designed to teach children specific things. They are a practical way to learn abstract concepts, otherwise these concepts will be difficult to digest. For example, children can use robots to learn geometry—maybe they need to program the robot to form a right angle, so they understand that 90º is a right angle, and if the robot continues to turn to the right, it can actually make a rectangular shape. These types of robots generally do not resemble animals or people, but have more practical shapes, such as cubes with wheels.

Can you describe what makes YOLO different?

YOLO is a robot whose purpose is to stimulate children's creativity in games. To this end, YOLO uses two techniques called "mirror" and "contrast". These two techniques are derived from creativity research and are used to develop convergent and divergent thinking, which are two different types of creative thinking that all of us have.

When YOLO uses mirroring, it means that the robot imitates the same game mode that children perform when manipulating the robot. So, if children move the robot to the right, YOLO will remember this action and then imitate it. If we imagine what this means in a story-telling environment, we can imagine a child moving the robot to the right because "the robot is going to school." When the robot imitated this action, the child understood "Yes, YOLO continues to school". Mirror technology stimulates convergent thinking, which is related to the elaboration and exploration of the details of a single idea.

When YOLO uses comparison, it means that the robot is comparing the child's game mode. Taking the same school as an example, if the child moves the robot to the right to indicate that it is going to school, the robot will move to the left to compare the movement. In the context of storytelling, children may think "Oh, what robots are afraid of at school!" This will change the story, and children may change their storytelling. Contrast technology stimulates divergent thinking, because children need to incorporate new robot behaviors into their stories in order for the stories to continue to be meaningful.

Note: The following video is an example of an original story created by a Portuguese kid playing YOLO. In order to protect the privacy of children, this story was made by an artist.

Why is YOLO's method so valuable?

The value of YOLO lies in the interaction with children. The main idea is to stimulate children's creativity through the interaction between children and YOLO. Although this robot uses creativity stimulation technology, it is also very simple, and children can play with it as an ordinary toy. YOLO combines the advantages of social robots with the known advantages of traditional toys. In general, when creating stories with YOLO, children are more creative.

The reason why we can create such a robot is because the children have participated in the entire design of the robot from the beginning. My main design principle for YOLO is that it can be adapted to children's world. The way I accomplish this is to test, test, and test YOLO with the kids until the robot is used naturally like a toy.

If you were asked to design a robot to perform the functions of YOLO without the involvement of children, what do you think would be different about this robot?

I believe YOLO will be very different. But I also believe that if another sample of children is introduced in the design process, YOLO will be very different. My main insight is that even if the appearance of the robot changes, the nature of YOLO's interaction with children will remain stable. This is because we can keep the key aspects of YOLO's operations unchanged, including the stimulation of creativity, open play, ease of use, and abstract non-anthropomorphic design. This means that YOLO can have different shapes and use different physical behaviors to express itself, while still using the same creative skills.

Why is it important to avoid personification?

The main reason is that if we design a robot that looks like a human, it is more difficult to meet expectations, because people expect the robot to behave like a human, but due to technical defects, this has never been the case. Staying away from designing humanoid robots will eventually become a gift in disguise, because this opens up a new space when thinking about robots: If they are not like us, how should robots look? I think this question is beautiful and can open the door to many creative and innovative applications of robots.

When you design with your child, how do you separate the physical robot design from the purpose and function of the robot?

YOLO's design started with the basic idea of ​​moving cubes. Many children's toys have geometric shapes, so I started to use origami techniques to make paper cubes. The paper cubes I made vary in size, and I asked the children to use the cubes as their characters to create a story. Then I just observe how the children play cubes, and based on their games, I made a design decision about YOLO.

For example, I began to notice that when children grasped a paper cube, they would grab the edge of the cube and make the edge rounded with use. I realized that these edges are not suitable for gripping, so I designed a new design with rounded edges for the children. This is the time to start designing the shape of the robot.

To design the behavior of YOLO, I listened to how children tell stories when they use paper cubes. They usually attribute specific personality traits to their paper cube roles. One character is grumpy, another character is shy, etc. This made me think that YOLO should also show personality. As a way to involve children in storytelling, I started to read research on personality, especially nonverbal behavior related to personality expression. The next step is to transform the personality requirements into the shape of a robot. For a grumpy character, YOLO will move very fast and in a large range. For a shy robot, YOLO will move slowly and at a low amplitude, almost saying "Don't look at me, I'm not here!"

A series of images showing different iterations of the YOLO robot, from sketches to paper models to designs of different sizes and shapes. Patricia Alves-Oliveira

How many iterations does the final design of YOLO need to go through?

I made a lot of improvements to the robot, changing the shape, size and multi-modal expression. I always let children test every change, and I draw inspiration from their behavior as inspiration for the next design iteration. For example, YOLO sometimes uses abstract sound as a way of expression. When the children interacted with this prototype version, they completely ignored the sound, and instead spoke on the robot, sometimes yelling at it. This shows that the robot's voice hindered their own expression in the story, so the voice was deleted, and YOLO is now a silent robot.

Another example is the use of touch as a social function. When I tested the first driving prototype, YOLO would start to move when the children were holding it, and the robot's movements scared the children. I remember a kid actually said, "The robot doesn't like me, it wants to walk away." After this test, I added a touch sensor to YOLO, so when it recognizes a touch, YOLO doesn’t move. Because a child is holding it to play. Only when the touch sensor no longer recognizes the touch, YOLO will start to move to ensure that the child's game will not be interrupted. This makes a huge difference in the interaction process.

A close-up image of the YOLO robot, showing wheels, touch sensors, and a small piece of plastic beard from the head of the robot, with LED lights Patricia Alves-Oliveira underneath

How do you incorporate multiple children (who may feel and want different things) into the design process of a single robot?

I included children aged 7-9 in the YOLO design. In this particular age group, children are at the same stage of development. They associate abstract concepts with specific situations and use locally existing objects as tools for learning and understanding the world. Despite differences in children's personalities and preferences, children of this age use, manipulate, and understand objects in very similar ways. This is also true in the context of robot design. Understanding the developmental stages of children helps me choose the activities and materials used in the design process to best define the design requirements of the robot.

When designing YOLO, I encountered a problem that I think many designers will face: when will the robot design be completed? It's easy to fall into feature creep and keep adding and adding features. To avoid this, I focus on design principles rather than design functions. The difference between principle and function is that when you design for a function, you add or delete the exact options that users require. This will make the design short-sighted.

For example, if YOLO starts to move while they are holding it, they will be scared. Designing for features means eliminating the robot's mobility. However, if we design according to principles, we need to have a deeper understanding of the interaction between children and robots. Once we have this, it is clear that the main issue here is not the movement of the robot, but the time the robot stays still. So children don't necessarily want a fixed robot; but a robot they can control, instead of eliminating the possibility of navigation, we added a touch sensor to prevent the robot from moving while being held.

Do you think this long process is worth it?

Building YOLO in my way is a 4-year journey that allows me to explore many aspects of how robots can be used to cultivate human inner capabilities (such as creativity). In the process of designing and building YOLO, I encountered many questions, such as what does it mean to build a robot for creativity? What methods do I need to develop to successfully incorporate children into the design of the robot? How to measure the success of using YOLO to stimulate creativity? Being able to answer all these questions is an important part of designing and manufacturing YOLO. I think while we use robots like YOLO to answer these questions, we are also contributing to many other fields, such as psychology, design, and engineering. land.

A paper detailing the design of YOLO won the best paper award on the design track of the HRI 2021 conference. You can see Patricia Alves-Oliveira talking about her research here.

IEEE explores the adoption of ICT, regulations and standards

The COVID-19 pandemic requires people to provide internet connectivity to underserved communities. Many people who can afford it are already able to work from home, learn from distance, and shop online, but not everyone does. According to data from the World Economic Forum, almost half of the world’s population does not have access to the Internet. Where it is accessible, it may be too expensive.

The IEEE Standards Association Connectivity and Telecommunications Practice is addressing this issue, studying the needs of the community and collaborating with other organizations. The organization has released a series of video interviews with industry professionals, researchers, and policy makers who are challenging industry professionals in Africa, India, Indonesia, and Mexico.

Design user-centric interfaces for rural communities. One obstacle to universal use is the lack of computer knowledge in some communities. To solve this problem, the IEEE Standards Association established the Rural Communication Industry Connection Program to study digital requirements and develop models for user interface design and implementation.

In this video hosted by the IEEE Standards Association Connection and Telecommunications Practice Chairperson, IEEE Associate Member Anmol Anubhai shares her real world and industry experience, and discusses how the program can help improve computer literacy.

Accelerate Africa's digital transformation through information and communication technology. According to the International Finance Corporation, the African continent has the least number of Internet connections. Broadband penetration rates in many African countries are less than 20%. The inability to obtain reliable and affordable electricity further complicates the problem.

Lacina Koné, Director-General and Chief Executive Officer of Smart Africa, said that other basic services need to be provided, including education, food safety and healthcare, which all play a role in the continent’s mission to connect unconnected people. In the video, Kone introduced the current efforts of African leaders to change the digital future of the African continent and accelerate socio-economic development through information and communication technology.

Connecting rural India through technical standards. Sandeep Agrawal, the team leader of the Bangalore Telematics Development Center, said that the Indian government has provided reliable Internet infrastructure for more than half of the rural residents, but these people are not using it enough because the cost of Internet access is too high. IEEE Senior Member Agrawal also discussed other challenges.

Almost half of the world’s population does not have access to the Internet

He also talked about two IEEE standard projects that he chaired to help expand the coverage of the Internet: IEEE P2872 Interoperable and Secure Public Wi-Fi Infrastructure and Architecture Working Group and Rural Communication Industry Connection Project.

Use ICT to protect data privacy in Indonesia. Many ICT users in Indonesia worry about their privacy because their data is owned by private operators. Benjamin Hsueh-Yung Koo, director of international relations at the iCenter at Tsinghua University in Beijing, said that one way to solve this problem is to use technical standards and data protocols. He studied policy and education challenges, and how technical standards support sustainable and trustworthy data governance.

Bridging the digital divide in Mexico through collaborative supervision. Since 2013, the country's internet connections have grown steadily. The Mexican government has played a key role in providing reliable infrastructure and affordable access, promoting public-private partnerships, and providing training to improve digital skills. Today, approximately 70% of Mexicans have access to wired or wireless internet. However, only 47% of the rural population can use it, compared with 76% of urban residents. Paola Cicero, Chief of Staff of the Federal Institute of Telecommunications in Mexico, discussed how to provide universal connectivity through the use of local IEEE resources and the development of collaborative regulations (such as sharing guidelines and best practices and defining cooperation mechanisms).

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This technical paper reviews the importance of accurate modeling of surface topography changes after electrochemical deposition for optimizing chemical mechanical polishing simulation. Siemens EDA and the American University of Armenia have collaborated to evaluate the use of machine learning (ML) modeling techniques to predict these complex terrain changes. Modeling the postECD surface profile using various ML methods allowed them to determine which models provided the best combination of runtime and accuracy.